View 83C196LC_186379.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ADVANCE INFORMATION
83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER
Automotive
s 22 MHz operation s 32 Kbytes of on-chip ROM (LC) 16 Kbytes of on-chip ROM (LD) s 1 Kbyte of on-chip register RAM (LC) 384 bytes of on-chip register RAM (LD) s 512 bytes of on-chip code RAM (LC only) s Register-to-register architecture s Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines s Full-duplex serial I/O port with dedicated baud-rate generator s Enhanced full-duplex, synchronous serial I/O port (SSIO)
s High-speed event processor array -- Six capture/compare channels -- Two compare-only channels -- Two 16-bit software timers s Programmable 8- or 16-bit external bus s Design enhancements for EMI reduction s Oscillator failure detection circuitry s SFR register that indicates the source of the last reset s Watchdog timer (WDT) s Cost reduced replacements for the 87C196JT and 87C196JR. s -40 C to +125 C ambient temperature s 52-pin PLCC package
12 MHz standard; 18 MHz and 22 MHz are speed premium
NOTE This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and 87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more flexible communication to other devices. The enhanced SSIO is compatible with Motorola's Serial Peripheral Interface (SPI) protocol and National's Microwire protocol. To optimize die size, the A/D converter was removed for use in those applications that use an off-chip A/D converter. The MCS(R) 96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs. The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming language.
COPYRIGHT (c) INTEL CORPORATION, 1996
December 1996
Order Number: 272805-001
83C196LC, 83C196LD -- AUTOMOTIVE
Port 6
Port 0
Watchdog Timer
Enhanced SSIO
Peripheral Addr Bus (10)
Peripheral Data Bus (16) Port 2
Memory Data Bus (16) Memory Addr Bus (16)
Bus Control
Bus Controller
AD15:0
SIO
Baud-rate Generator
Bus-Control Interface Unit Queue Microcode Engine
Peripheral Transaction Server Interrupt Controller EPA
6 Capture/ Compare Channels 2 Timers 2 Compare-only Channels
Source (16) Port 1,6 Memory Interface Unit
ALU
Register RAM 1 Kbyte (LC) 384 Bytes (LD)
Destination (16)
Code/Data RAM 512 Bytes (LC only)
ROM 32 Kbytes (LC) 16 Kbytes (LD)
A seventh capture/compare channel (EPA7) is available as a software timer. It is not connected to a package pin.
A3383-01
Figure 1. 83C196LC, 83C196LD Block Diagram
2
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
1.0
NOMENCLATURE OVERVIEW
X
Te
XX
Pa ck
8
X
X
XXXXX
XX
ed pe eS vic De ily am tF uc od on Pr ati ns rm tio nfo Op sI ry es mo oc Pr Me m ra og Pr
Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed Options A N 3 C 196Lx no mark 18 22 Description Automotive operating temperature range (-40 C to 125 C ambient) with Intel standard burn-in. PLCC Internal ROM CHMOS 8XC196Lx family of products 12 MHz 18 MHz 22 MHz
ADVANCE INFORMATION
mp er
ag ing Op n tio
atu re an
Figure 2. Product Nomenclature
ur dB
s
nin Op
tio ns
A2815-01
3
83C196LC, 83C196LD -- AUTOMOTIVE
2.0
PINOUT
AD14 / P4.6 AD13 / P4.5 AD12 / P4.4 AD11 / P4.3 AD10 / P4.2 AD9 / P4.1 AD8 / P4.0 AD7 / P3.7 AD6 / P3.6 AD5 / P3.5 AD4 / P3.4 AD3 / P3.3 AD2 / P3.2
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47
AD15 / P4.7 P5.2 / WR# / WRL# P5.3 / RD# VPP VSS P5.0 / ADV# / ALE VSS XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P6.5 / SD0 P6.4 / SC0
N83C196LC N83C196LD View of component as mounted on PC board
46 45 44 43 42 41 40 39 38 37 36 35 34
P6.1 / EPA9 P6.0 / EPA8 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 VCC VSS P0.7 P0.6 P0.5 P0.4 P0.3
AD1 / P3.1 AD0 / P3.0 RESET# EA# VSS VCC P2.0 / TXD P2.1 / RXD P2.2 / EXTINT P2.4 P2.6 / ONCE# P2.7 / CLKOUT P0.2
21 22 23 24 25 26 27 28 29 30 31 32 33
A3403-01
Figure 3. 83C196LC, 83C196LD 52-pin PLCC Package Table 2. 83C196LC, 83C196LD 52-pin PLCC Package Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 VSS P5.0/ADV#/ALE VSS VPP P5.3/RD# P5.2/WR#/WRL# AD15/P4.7 AD14/P4.6 AD13/P4.5 AD12/P4.4 AD11/P4.3 AD10/P4.2 AD9/P4.1 Name Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 Name AD8/P4.0 AD7/P3.7 AD6/P3.6 AD5/P3.5 AD4/P3.4 AD3/P3.3 AD2/P3.2 AD1/P3.1 AD0/P3.0 RESET# EA# VSS VCC Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 Name P2.0/TXD P2.1/RXD P2.2/EXTINT P2.4 P2.6/ONCE# P2.7/CLKOUT P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSS Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 VCC P1.3/EPA3 P1.2/EPA2/T2DIR P1.1/EPA1 P1.0/EPA0/T2CLK P6.0/EPA8 P6.1/EPA9 P6.4/SC0 P6.5/SD0 P6.6/SC1 P6.7/SD1 XTAL2 XTAL1 Name
4
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
Table 3. Pin Assignment Arranged by Functional Categories Addr & Data Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Input Name P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Pin 33 34 35 36 37 38 Pin 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Input/Output Name P1.0/EPA0/T2CLK P1.1/EPA1 P1.2/EPA2/T2DIR P1.3/EPA3 P2.0/TXD P2.1/RXD P2.2 P2.4 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 Pin 44 43 42 41 27 28 29 30 31 32 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 VCC VCC VPP VSS VSS VSS VSS Power & Ground Name Pin 26 40 4 1 3 25 39 P4.7 P5.0 P5.2 P5.3 P6.0/EPA8 P6.1/EPA9 P6.4/SC0 P6.5/SD0 P6.6/SC1 P6.7/SD1 Input/Output (Cont'd) Name Pin 7 2 6 5 45 46 47 48 49 50 RD# WR#/WRL# Bus Control & Status Name ADV#/ALE Pin 2 5 6 EA# EXTINT ONCE# RESET# XTAL1 XTAL2 Processor Control Name CLKOUT Pin 32 24 29 31 23 52 51
ADVANCE INFORMATION
5
83C196LC, 83C196LD -- AUTOMOTIVE
3.0
SIGNALS
Table 4. Signal Descriptions Name Type I/O Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0-15 are presented on the bus and can be latched using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred. AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0. Description
AD15:0
ADV#
O
Address Valid This active-low output signal is asserted only during external memory accesses. ADV# indicates that valid address information is available on the system address/data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. An external latch can use this signal to demultiplex the address from the address/data bus. A decoder can also use this signal to generate chip selects for external memory. ADV# shares a package pin with P5.0 and ALE.
ALE
O
Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. An external latch can use this signal to demultiplex the address from the address/data bus.
CLKOUT
O
Output Output of the internal clock generator. The CLKOUT frequency is 1/2 the oscillator input frequency (FXTAL1). CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7
EA#
I
External Access This input determines whether memory accesses to special-purpose and program memory partitions are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to externalmemory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# is sampled and latched only on the rising edge of RESET#. Changing the level of EA# after reset has no effect.
EPA9:8 EPA3:0
I/O
Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. The EPA signals share package pins with the following signals: EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3, EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1. EPA7 does not connect to a package pin. It cannot be used to capture an event, but it can function as a software timer. EPA6:4 are not implemented.
6
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
Table 4. Signal Descriptions (Continued) Name EXTINT Type I External Interrupt In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum high time is one state time. In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation. The interrupt does not need to be enabled. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT shares a package pin with P2.2. ONCE# I On-circuit Emulation Holding ONCE# low during the rising edge of RESET# places the microcontroller into on-circuit emulation (ONCE) mode. This mode puts all pins into a high-impedance state, thereby isolating the microcontroller from other components in the system. The value of ONCE# is latched when the RESET# pin goes inactive. While the microcontroller is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the microcontroller by pulling the RESET# signal low. To prevent inadvertent entry into ONCE mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the VIH specification. ONCE# shares a package pin with P2.6. P0.7:2 P1.3:0 I I/O Port 0 This is a high-impedance, input-only port. Port 0 pins should not be left floating. Port 1 This is a standard bidirectional port that shares package pins with individually selectable special-function signals. Port 1 shares package pins with the following signals: P1.0/EPA0/T2CLK, P1.1/EPA1, P1.2/EPA2/T2DIR, P1.3/EPA3. P2.7:6 P2.4 P2.2:0 I/O Port 2 This is a standard bidirectional port that shares package pins with individually selectable special-function signals. P2.6 is multiplexed with the ONCE function. If this pin is held low during reset, the device will enter ONCE mode, so exercise caution if you use this pin for input. If you choose to configure this pin as an input, always hold it lowhigh during reset and ensure that your system meets the VIH specification to prevent inadvertent entry into ONCE mode. Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD, P2.2/EXTINT, P2.6/ONCE#, P2.7/CLKOUT. P3.7:0 I/O Port 3 This is a memory-mapped, 8-bit, bidirectional port with programmable opendrain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0. Description
ADVANCE INFORMATION
7
83C196LC, 83C196LD -- AUTOMOTIVE
Table 4. Signal Descriptions (Continued) Name P4.7:0 Type I/0 Port 4 This is a memory-mapped, 8-bit, bidirectional port with open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8. P5.3:2 P5.0 I/O Port 5 This is a memory-mapped, bidirectional port. Port 5 shares package pins with the following signals: P5.0/ADV#/ALE, P5.2/WR#/WRL#/PLLEN, and P5.3/RD#. P5.1 and P5.7:4 are not implemented. P6.7:4 P6.1:0 O Port 6 This is a standardbidirectional port. Port 6 shares package pins with the following signals: P6.0/EPA8/COMP0, P6.1/EPA9/COMP1, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1. RD# O Read Read-signal output to external memory. RD# is asserted during external memory reads. RD# shares a package pin with P5.3. RESET# I/O Reset A level-sensitive reset input to, and an open-drain system reset output from, the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown and idle modes, asserting RESET# causes the microcontroller to reset and return to normal operating mode. After a reset, the first instruction fetch is from 2080H. RXD I/O Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1. SC1:0 SD1:0 I/O I/O Clock Pins for SSIO0 and 1 SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6. Data Pins for SSIO0 and 1 These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure SDx as a complementary output signal. For receptions, configure SDx as a high-impedance input signal. SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7. T2CLK I Timer 2 External Clock External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature counting mode. T2CLK shares a package pin with P1.0 and EPA0. Description
8
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
Table 4. Signal Descriptions (Continued) Name T2DIR Type I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. It is also used in conjunction with T2CLK for quadrature counting mode. T2DIR shares a package pin with P1.2 and EPA2. TXD O Transmit Serial Data In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD shares a package pin with P2.0. VCC VPP PWR PWR Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Powerdown Exit VPP causes the device to exit powerdown mode when it is driven low for at least 50 ns. Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks, but not the internal oscillator. If you do not plan to use the powerdown feature, connect VPP to VCC. VSS GND Digital Circuit Ground These pins supply ground for the digital circuitry. Connect each VSS pin to ground through the lowest possible impedance path. WR# O Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# shares a package pin with P5.2 and WRL#.
Description
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
WRL#
O
Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# shares a package pin with P5.2 and WR#.
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
ADVANCE INFORMATION
9
83C196LC, 83C196LD -- AUTOMOTIVE
Table 4. Signal Descriptions (Continued) Name XTAL1 Type I Description Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1. XTAL2 O Inverted Output for the Crystal/Resonator Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator.
10
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
4.0
ADDRESS MAP
Table 5. Address Map
Hex Address Range LC FFFF A000 9FFF 2080 207F 2000 1FFF 1FE0 1FDF 1F00 1EFF 1C00 1BFF 0600 05FF 0400 -- 03FF 0100 00FF 0000 LD FFFF 6000 5FFF 2080 207F 2000 1FFF 1FE0 1FDF 1F00 1EFF 1C00 1BFF 0600 -- 05FF 0180 017F 0100 00FF 0000
Description External device (memory or I/O) connected to address/data bus Program memory (internal nonvolatile or external memory); see Note 1 Special-purpose memory (internal nonvolatile or external memory) Memory-mapped SFRs Peripheral SFRs External device (memory or I/O) connected to address/data bus; (future SFR expansion; see Note 2) External device (memory or I/O) connected to address/data bus Internal code or data RAM External device (memory or I/O) connected to address/data bus Upper register file (general-purpose register RAM) Lower register file (register RAM, stack pointer, and CPU SFRs)
Addressing Modes Indirect or indexed Indirect or indexed Indirect or indexed Indirect or indexed Indirect, indexed, or windowed direct Indirect or indexed Indirect or indexed Indirect or indexed Indirect or indexed Indirect, indexed, or windowed direct Direct, indirect, or indexed
NOTES: 1. After a reset, the microcontroller fetches its first instruction from 2080H. 2. The content or function of these locations may change in future microcontroller revisions, in which case a program that relies on a location in this range might not function properly.
5.0
ELECTRICAL CHARACTERISTICS
NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS
Storage temperature ............................... -60 C to +150 C Supply voltage with respect to VSS ............. -0.5 V to +13.0 V Power dissipation ......................................................... 0.5 W
OPERATING CONDITIONS
TA (Ambient temperature under bias)........ -40 C to +125 C VCC (Digital supply voltage) ......................... 4.50 V to 5.50 V FXTAL1 (Oscillator frequency)....................... 4 MHz to 22 MHz
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
ADVANCE INFORMATION
11
83C196LC, 83C196LD -- AUTOMOTIVE
5.1
DC Characteristics
Table 6. DC Characteristics at VCC = 4.5V - 5.5V
Symbol ICC
Parameter VCC supply current (-40 C to +125 C ambient) Active mode supply current (typical) Idle mode current Powerdown mode current Input low voltage (all pins) Input high voltage (all pins) Output low voltage (outputs configured as complementary) Output high voltage (outputs configured as complementary) Input leakage current (standard inputs, ports 3 & 4) Input leakage current (port 0) Input high current (NMI pin) Output high voltage in reset Output high current in reset Reset pullup resistor
Min
Typical
Max 88
Units mA
Test Conditions FXTAL1 = 20 MHZ, VCC = VPP = 5.5V (While device is in reset)
ICC1 IIDLE IPD VIL VIH VOL
55 20 50 -0.5V 0.7 VCC 40 TBD 0.3 VCC VCC + 0.5 0.3 0.45 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5 10
mA mA A V V V V V V V V A IOL = 200 A (Notes 3, 5) IOL = 3.2 mA IOL = 7.0 mA IOH = -200 A (Notes 3, 5) IOH = -3.2 mA IOH = -7.0 mA VSS VIN VCC (Note 2) VSS VIN VREF VSS VIN VCC IOH = -15 A (Note 1) VOH2 = VCC - 1.0V VOH2 = VCC - 2.5V VOH2 = VCC - 4.0V FXTAL1 = 20 MHz, VCC = VPP = 5.5V VCC = VPP = 5.5V (Note 6)
VOH
ILI
ILI1 IIH VOH2 IOH2
2.0 +175 VCC - 1V -25 -45 -50 6K -120 -240 -280 65K
A A V A A A
RRST
NOTES: 1. All bidirectional pins except CLKOUT. CLKOUT is not pulled weakly high in reset. Bidirectional pins include ports 1-6. 2. Standard input pins include XTAL1, EA#, RESET#, P0.7:2, and ports 1-6 when configured as inputs. 3. All bidirectional pins when configured as complementary outputs. 4. Device is static and should operate below 1 Hz, but is only tested down to 4 MHz. 5. Maximum IOLor IOH currents per pin will be characterized and published at a later date. Target values are 10 mA. 6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and VCC = 5.0V.
12
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
Table 6. DC Characteristics at VCC = 4.5V - 5.5V (Continued) Symbol CS RWPU Parameter Pin capacitance (any pin to VSS) Weak pullup resistance (approximate) 150K Min Typical Max 10 Units pF Test Conditions FTEST = 1.0 MHz (Note 6)
NOTES: 1. All bidirectional pins except CLKOUT. CLKOUT is not pulled weakly high in reset. Bidirectional pins include ports 1-6. 2. Standard input pins include XTAL1, EA#, RESET#, P0.7:2, and ports 1-6 when configured as inputs. 3. All bidirectional pins when configured as complementary outputs. 4. Device is static and should operate below 1 Hz, but is only tested down to 4 MHz. 5. Maximum IOLor IOH currents per pin will be characterized and published at a later date. Target values are 10 mA. 6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and VCC = 5.0V.
ADVANCE INFORMATION
13
83C196LC, 83C196LD -- AUTOMOTIVE
5.2
AC Characteristics
Test Conditions: capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FXTAL1 = 22 MHz. Table 7. AC Characteristics Symbol Parameter Min Max Units MHz(1) ns ns(2) ns ns ns ns ns ns ns ns ns 20 ns ns TXTAL1 + 25 5 TXTAL1 - 10 -10 TXTAL1 - 23 -10 TXTAL1 - 20 TXTAL1 - 25 TXTAL1 - 10 TXTAL1 - 30 TXTAL1 - 30
(4) (4)
The 83C196LC, 83C196LD meets these specifications FXTAL1 TXTAL1 TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHAX TRHAX Oscillator Frequency Oscillator Period (1/FXTAL1) XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling to ALE Rising ALE Falling to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Low Address Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# Low to RD# High RD# High to ALE Rising RD# Low to Address Float ALE Low to WR# Low CLKOUT Low to WR# Falling Edge Data Valid to WR# High CLKOUT High to WR# Rising Edge WR# Low to WR# High Data Hold after WR# High WR# High to ALE High AD15:8 Hold after WR# High AD15:8 Hold after RD# High 4.0 45.45 20 2 TXTAL1 TXTAL1 - 10 -10 -20 4 TXTAL1 TXTAL1 - 10 TXTAL1 - 15 TXTAL1 - 40 TXTAL1 - 30 -10 TXTAL1 - 5 TXTAL1 TXTAL1 + 10 TXTAL1 + 15 15 15 22.0 200 110
ns(3) ns(5) ns
20
ns ns
15
ns ns ns ns(3) ns ns
TXTAL1 + 15
NOTES: 1. Testing is performed at 4 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. TRLAZ (max) = 5 ns by design.
14
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
Table 7. AC Characteristics (Continued) Symbol Parameter Min Max Units The external memory system must meet these specifications TAVDV TRLDV TCLDV TRHDZ TRXDX Address Valid to Input Data Valid RD# Low to Input Data Valid CLKOUT Low to Input Data Valid RD# High to Input Data Float Data Hold after RD# Inactive 0 3 TXTAL1 - 55 TXTAL1 - 22 TXTAL1 - 50 TXTAL1 ns ns ns ns ns
NOTES: 1. Testing is performed at 4 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. TRLAZ (max) = 5 ns by design. Table 8. AC Timing Symbol Definitions Character A C D L Q R W Character H L V X Z High Low Valid No Longer Valid Floating (low impedance) AD15:0 CLKOUT AD15:0, AD7:0 ALE AD15:0, AD7:0 RD# WR#, WRL# Condition Signal(s)
ADVANCE INFORMATION
15
83C196LC, 83C196LD -- AUTOMOTIVE
TXTAL1 XTAL1 CLKOUT TCLLH ALE/ADV# TLHLL TLLRL RD# TAVLL AD15:0 (read) WR# AD15:0 (write) AD15:8 (8-bit data bus) TQVWH Address Out Data Out TWHQX Address Out TWHAX, TRHAX High Address Out
A4320-01
TCLCL
TXHCH
TCHCL
TLLCH TLHLH
TRLRH
TRHLH
TRLAZ TLLAX TRLDV Data In TLLWL TWLWH
TRHDZ
Address Out TAVDV
TWHLH
Figure 4. System Bus Timing
16
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
5.3
AC Characteristics -- Serial Port, Shift Register Mode
Test Conditions: TA = -40C to +125C; VCC = 5.0V 10%; VSS = 0.0V; Load Capacitance = 100 pF Table 9. Serial Port Timing -- Shift Register Mode Symbol TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ

Parameter Serial port clock period Serial port clock falling edge to rising edge Output data setup to clock high Output data hold after clock high Next output data valid after clock high Input data setup to clock high Input data hold after clock high Last clock high to output float
Min 8 TXTAL1 4 TXTAL1 - 50 3 TXTAL1 2 TXTAL1 - 50
Max
Units ns
4 TXTAL1 + 50
ns ns ns
2 TXTAL1 + 50 2 TXTAL1 + 200 0 5 TXTAL1
ns ns ns ns
Parameter not tested.
TXLXL TXDx TQVXH RXDx (Out) RXDx (In)
0 1 2
TXLXH
3
TXHQV
4
TXHQX
5 6
TXHQZ
7
TDVXH
Valid Valid Valid
TXHDX
Valid Valid Valid Valid Valid
A2080-03
Figure 5. Serial Port Waveform -- Shift Register Mode
ADVANCE INFORMATION
17
83C196LC, 83C196LD -- AUTOMOTIVE
5.4
AC Characteristics -- Synchronous Serial Port
Table 10. Synchronous Serial Port Timing
Symbol TCLCL TCLCH TD1VD TCXDV TCXDX TDVCX TDXCX
Parameter Synchronous Serial Port Clock period Synchronous Serial Port Clock falling edge to rising edge Setup time for MSB output Setup time for D6:0 output Output data hold after clock high Setup time for input data Input data hold after clock high
Min TBD TBD TBD 1.5t + 20 0.5t 10 t+5
Max TBD TBD
Units ns ns ns ns ns ns ns
SCx (normal transfers)
1
2
3
4
5
6
7
8
TCHCL TCLCH TCHCH
STE Bit
SDx (out)
MSB
D6
D5
D4
D3
D2
D1
D0
TD1DV
SDx (in)
valid valid valid valid valid valid valid valid
TDVCX
SCx (handshaking transfers) 1 2 3 4 5 6 7
TDXCX
8
TCXDX
TCXDV
Slave Receiver Pulls SCx low
Assumes that the SSIO is configured to sample incoming data on the rising clock edge and sample outgoing data on the falling clock edge, and that the SSIO is configured to pull the clock signal low while the channel is idle.
A3233-02
Figure 6. Synchronous Serial Port
18
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
5.5
External Clock Drive
Table 11. External Clock Drive Symbol Parameter Oscillator Frequency Oscillator Period (TXTAL1) High Time Low Time Rise Time Fall Time Min 4.0 45.45 0.35 TXTAL1 0.35 TXTAL1 Max 22 200 0.65 TXTAL1 0.65 TXTAL1 10 10 Units MHz ns ns ns ns ns
1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL
TXHXX 0.7 VCC + 0.5 V XTAL1
TXLXH TXLXX 0.3 VCC - 0.5 V 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V TXLXL
TXHXL
A2119-03
Figure 7. External Clock Drive Waveforms
ADVANCE INFORMATION
19
83C196LC, 83C196LD -- AUTOMOTIVE
5.6
Test Output Waveforms
3.5 V
2.0 V Test Points 0.8 V
2.0 V 0.8 V
0.45 V
Note: AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A2120-04
Figure 8. AC Testing Input, Output Waveforms
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-03
Figure 9. Float Waveforms
20
ADVANCE INFORMATION
AUTOMOTIVE -- 83C196LC, 83C196LD
6.0 THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information. Table 12. Thermal Characteristics Package Type 52-pin PLCC JA 42C/W JC 15C/W
NOTES: 1. JA = Thermal resistance between junction and the surrounding environment (ambient). Measurements are taken 1 ft. away from case in static air flow environment. JC = Thermal resistance between juction and package surface (case). 2. All values of JA and JC may fluctuate depending on the environment (with or without airflow, and how much airflow) and microcontroller power dissipation at temperature of operation. Typical variations are 2C/W. 3. Values listed are at a maximum power dissipation of 0.50 W.
7.0 DESIGN CONSIDERATIONS
The 83C196LC and 83C196LD are pin-compatible replacements for the 87C196JT and 87C196JR microcontrollers with the following exceptions. * * The synchronous serial I/O port was enhanced to provide more flexible communication to other devices; however, it remains compatible with the 87C196JT and JR non-enhanced SSIO. The A/D converter was removed to optimize die size.
Follow these recommendations to help maintain hardware and software compatibility between 52-pin, 68-pin, and future microcontrollers. * * * * * Bus width. Since the 83C196LC and LD have neither a WRH# nor a BUSWIDTH pin, the microcontrollers cannot dynamically switch between 8- and 16-bit bus widths. Program the CCBs to select 8-bit bus mode. Wait states. Since the 83C196LC and LD have no READY pin, the microcontrollers cannot rely on a READY signal to control wait states. Program the CCBs to limit the number of wait states (0, 1, 2, or 3). Write cycle during reset. If the microcontroller is reset during a write cycle, the contents of the external memory device may be corrupted. EPA7. This function exists in the83C196LC and LD, but the associated pin is omitted. You can use this channel either as a software timer or to reset the timers. EPA timer reset/write conflict. If an EPA channel resets the timer at the same time your code writes to the timer, it is indeterminate which action takes precedence. If your code uses an EPA channel to reset a timer, do not write to the timer. Valid time matches. The timer must increment or decrement to the compare value for a valid match to occur. Writing the compare value to the timer will not cause a match. Resetting the timer also will not cause a match when the compare value is zero. NMI. Since the 83C196LC and LD have no NMI pin, the nonmaskable interrupt is not supported. Initialize the NMI vector (at location 203EH) to point to a RET instruction. This method provides glitch protection only.
*
*
ADVANCE INFORMATION
21
83C196LC, 83C196LD -- AUTOMOTIVE
* I/O port pins. The following port pins do not exist in the 83C196LC and LD: P0.0-P0.1, P1.4-P1.7, P2.3 and P2.5, P5.1 and P5.4-P5.7, P6.2 and P6.3. Software can still read and write the associated Px_REG, Px_MODE, and Px_DIR registers. Configure the registers for the removed pins as follows: -- Clear the corresponding Px_DIR bits. (Configures pins as complementary outputs.) -- Clear the corresponding Px_MODE bits. (Selects I/O port function.) -- Write either "0" or "1" to the corresponding Px_REG bits. (Effectively ties signals low or high.) -- Do not use the bits associated with the removed port pins for conditional branch instructions. Treat these bits as reserved. * P6.7:4. A value written to any of the upper four bits of P6_REG (bits 4-7) is held in a buffer until the corresponding P6_MODE bit is cleared, at which time the value is loaded into the P6_REG bit. A value read from a P6_REG bit is the value currently in the register, not the value in the buffer. Therefore, any change to a P6_REG bit can be read only after the corresponding P6_MODE bit is cleared. Reading reserved memory locations. The 87C196JT and JQ implement a precharged peripheral bus within the microcontroller that returns a logic one when reserved bits are read. The 83C196LC and LD use a driven bus within the microcontroller that returns the last value driven on the peripheral data bus when reserved bits are read.
*
8.0
83C196LC, 83C196LD ERRATA
There is no known device errata at this time.
9.0 DATASHEET REVISION HISTORY
This datasheet is valid for devices with an "A" at the end of the topside field process order (FPO) number. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices.
22
ADVANCE INFORMATION

▲Up To Search▲

Price & Availability of 83C196LC

	To Download 83C196LC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .